The invention relates to a switching FET circuit and to a method of operation of such a circuit, for example for use in a synchronous dc-dc voltage converter.
Circuits involving switching FETs are known. Examples include direct current (dc) to dc converters which are generally used to convert from one dc voltage level to another, for example to provide a 1.5V voltage rail from a 12V voltage supply.
One type of converter, a synchronous dc-dc converter, is illustrated schematically in FIG. 1. input voltage Vin is applied between input terminals 2, 4. A pair of transistors, here field effect transistors 6, 8, are connected between the input terminals 2, 4. The transistor 6 adjacent to the input terminal 4 is known as the control FET or high side transistor, and the transistor 8 adjacent to the ground is know as the synchronous (sync) FET or low side transistor. The high side is relatively more positive than the low side, though it is not necessary that either the high or the low side has any particular relationship to ground.
The node between the transistors 6, 8 is known as the switch node 10. The switch node feeds through an inductor 12 and across a capacitor 14 to an output 16.
The control and sync FETs are driven by respective drivers 30,32.
A control circuit 18 has one input on an input control terminal 20 and another input fed from the output 16 via a feedback path 22. The control circuit 18 supplies control signals to control the FETs 6,8 to maintain a constant voltage at the output by switching transistors 6,8 off and on alternately. The control signals are alternating signals which cause the control and sync FETs to conduct alternately. The mark-space ratio is varied, i.e. the ratio of the time for which the control FET conducts to the time the sync FET conducts is modulated, to achieve the desired voltage on the output 16.
Examples of such dc-dc converters include those presented in WO98/49607 to Intel Corporation and U.S. Pat. No. 5,479,089 to Lee.
One feature of synchronous dc-dc converters is that it is not generally desired to switch on both high and low side transistors 6,8 simultaneously. If both transistors are on, the input voltage is short-circuited by current passing directly between the two input terminals 2,4 through the control and sync FETs. The phenomenon known as xe2x80x9cshoot-throughxe2x80x9d. Accordingly, the control circuit 18 is generally arranged to ensure that only one of the two transistors 6,8 is on at a time.
This is conventionally carried out by monitoring two voltages. The voltage at the switch node 10 is monitored to prevent the switching on of the low side transistor 8 until the high side transistor 6 is switched off. The voltage at the gate 24 of the low side transistor 8 is monitored to prevent the high side transistor switching on until the low side transistor 8 is switched off. WO98/49607 describes a circuit of this type, as does U.S. Pat. No. 5,479,089 to Lee.
The dead time when neither FET is conducting depends on the transistor threshold voltage and the capacitance of the sync FET, which vary widely due to manufacturing spread of parameters of the chosen FET, as well as according to the individual choice of FET. This means that a control IC has to use conservative estimates of these parameters to produce a dead time that will avoid shoot through. This is generally a longer dead time than would be possible if the control circuit were optimised for the specific FETs used.
The present trend is to increase switching and clock speeds, which increases the significance of the dead time during which neither high or low side transistor 6,8 is on. It would be beneficial to reduce this time.
A further disadvantage occurs in the case that a plurality of FETs in parallel are used in place of the single high and low side transistors. The parallel FETs never switch at exactly the same time due to different gate resistances and other parameters caused again by manufacturing variations or variability in the circuit in which the FETs are provided. Thus, it becomes difficult to correctly determine when all of the high side or low side FETs are switched off and accordingly when the other FETs can be switched on. The solution generally adopted is to include a gate resistor in the circuit, but this slows down the switching of the FETs and increases switching losses, especially at high frequencies. Accordingly, it would be beneficial to provide a circuit arrangement that could more easily use parallel FETs.
According to the invention there is provided a switching circuit for switching an input dc voltage of predetermined polarity applied to input voltage terminals, comprising a high side package and a low side package each having a logic input and a switch connected between switching outputs, the switching outputs of the high and low side packages being connected in series between the input voltage terminals; a pulse width modulator connected to the logic inputs of the packages for supplying an alternating control signal to the logic inputs for switching the high and low side switches alternately; wherein each of the high and low side packages contains logic circuitry for controlling the respective switch based solely on the voltages on the respective logic input and respective switching outputs to prevent the switches in the high and low side packages from conducting at the same time.
Thus, shoot through is prevented without the need for providing complex circuitry to pass control signals between the high and low side circuits. The only control signal needed is the alternating pulse width modulated (PWM) control signal, which may be at logic levels. Since the driver circuits in the high and low side components are not reliant on signals from the other of the high and low side components the switching can be speeded up and the dead time in which neither of the switches are conducting can be reduced.
The switches may be FETs.
The node connecting the high and low side package is known as the switch node. The logic circuitry in each of the packages may include a sense circuit that controls the switching of the corresponding switch based on the voltage at the switch node and the voltage input.
In preferred embodiments, the sense circuits include an edge detector for detecting a voltage edge of opposite polarity to the predetermined polarity and for switching on the corresponding FET only after the voltage edge is detected.
Alternatively, the logic circuits may implement a delay after the control signal alternates before switching on the corresponding FET.
The driver circuit may be isolated from the control circuit and the low voltage side of the driver circuit may be directly connected to the source of the corresponding FET. In this way the area of the circuit that drives the gate can be minimised, which minimises the gate-source loop inductance, contributing to faster rise and fall times of the gate-source voltage. Further, any parasitic inductance in the source connection does not cause a reduction in the gate-source voltage with consequent slower switching at turn-on of the FET.
The drivers may be directly connected to the gates of the corresponding FETs without the need for a resistor between driver and gate. Such a resistor may be needed in prior designs in which switching on of the control FET is triggered by monitoring the gate voltage of the sync FET.
The high and low side components can readily be arranged in parallel, since each includes its own circuitry for avoiding shoot through.
By integrating a driver with each FET in a corresponding package, board space may be reduced and board design simplified. Each FET can now be considered as a device that takes a digital input and automatically controls its gate drive to ensure that it conducts at the appropriate time to prevent shoot-through and minimise dead time.
The high side component may include an internal bootstrap diode and be isolated from the control circuit. This permits the voltage used on the FET not to match that used to drive the control and driver circuits.
An internal regulator may be provided to ensure safe operating voltages for the gate drive and to provide power to any level-shifters included.
Thermal protection may be included to shut the FET down directly in the event of a fault condition without any external monitoring.
Increased power may more readily be provided. For example, on a multilayer FR4 PCB populated with surface mount packages, each device is limited to about 3 W of dissipation. To increase power, it is necessary to include more phases, i.e. to drive additional FETs at different phases by using a phase-shifted PWM signal, since adding additional packages by paralleling devices is dangerous because of the risk of shoot-through or cross-conduction. By sensing at the switch node of each component paralleling is possible which enables the solution of the invention to be readily scaled.
The invention also relates to the high and low side components themselves. Accordingly, in another aspect the invention relates to a high side component for use in a switching circuit for switching an input dc voltage of predetermined polarity, wherein the high side component includes a package comprising: a FET having source, drain and gate; a driver controlling the gate; a voltage input connected to the drain for inputting the high voltage side of the input dc voltage; an output connected to the source; a logic input for accepting an alternating control signal; and a logic circuit that controls the driver to switch the high side FET based on the logic input, the logic circuit including a sense circuit that detects the voltage on the source of the FET and controls the switching of the FET based on the logic input for preventing the FET from conducting at the same time as a low side FET connected between the output and the ground side of the input dc voltage.
In a yet further aspect the invention relates to a low side component for use in a switching circuit for switching an input dc voltage of predetermined polarity, wherein the low side component includes a package comprising: a FET having source, drain and gate; a driver controlling the gate, a voltage input connected to the source for inputting the low voltage side of the input dc voltage; an output connected to the drain; a logic input for accepting an alternating control signal; a logic circuit that controls the driver to switch the FET based on switch on the logic input, the logic circuit including a sense circuit that detects the voltage on the drain of the FET and controlling the switching of the FET based on the logic input for preventing the FET from conducting at the same time as a high side FET connected between the high voltage side of the input dc voltage and the output, wherein the driver is isolated from the logic circuit and the driver is referenced directly to the source.
The invention also relates to a method of operating a synchronous dc-dc converter circuit having a high side component including a control FET connected between an input dc terminal and a switch node and a low side component including a sync FET connected between the switch node and a ground terminal including: driving high side and low side packages alternately by an alternating control signal; and preventing the sync and control FETs from being switched on simultaneously. This is achieved by, in the high side package in response to a change in polarity of the alternating control signal from a first polarity to a second polarity, switching off the control FET, and in response to a change of polarity of the alternating signal from the second polarity to the first polarity delaying and then switching on the control FET; and in the low side package in response to a change in polarity of the alternating signal from the second polarity to the first polarity switching off the sync FET, and in response to a change of polarity of the alternating signal from the first polarity to the second polarity delaying and then switching on the sync FET.
The step of delaying may include delaying for a predetermined time.
Alternatively, the step of delaying may include waiting for a negative edge on the voltage on the switch node and then triggering the switching on of the respective FET.